1. Field of the Invention
The present invention generally relates to means for testing the constituent recirculating type memory elements of certain computer memory arrays and, more particularly, to apparatus for quickly locating the subdivisions of said array.
2. Description of the Prior Art
Copending patent application Ser. No. 163,373 for Recirculating Loop Memory Array Tester, filed June 26, 1980, in the name of F. J. Aichelmann, Jr. and assigned to the present assignee discloses a technique for rapidly initializing and testing memory arrays of multiple CCD loops accessible via single input-output (I/O) pins. Briefly, the input data gate for each loop is modified to receive a bulk store input signal which, when present, allows the same data to be inputted simultaneously to all loops in parallel. All loops are loaded (initialized) with identical data in the same time required to load a single addressed loop. Where the loaded data is test data, the stored data is verified by the provision of a comparison gate. The comparison gate receives an output from each loop as the loop recirculates the stored data. The loop outputs are ANDED by the comparison gate to produce a data verification signal only in the event that all of the data received from each loop is identical to that from all other loops on a bit-by-bit basis. A distinctive signal also is generated in the event that any one or more loops is non-identical to the data bits from all other loops. However, the technique disclosed in the aforementioned patent application does not provide for the determination of the location(s) of the faulty bit(s).